1. Field of the Invention
This invention generally relates to a semiconductor device and a fabrication method thereof, and more specifically, to a semiconductor device having conductive bumps and a fabrication method thereof.
2. Description of Related Art
Mainly, the conventional flip chip semiconductor package technique with solder bumps formed on solder pads of chips, and via the solder bumps, the chips are directly and electrically connected to a chip carrier. In comparison with the wire bonding technique, such flip chip technique has shorter circuit route, and better electricity quality, and it also has better heat dissipation efficiency for chips as its availability to be designed with uncovered chips.
As disclosed in U.S. Pat. Nos. 6,111,321, 6,107,180, and 6,586,323, an under bump metallurgy (UBM) is formed in such flip chip technique before the formation of the solder bumps in order to have the solder bumps steadily glued onto the solder pads of the chip as disclosed in the prior art. However, daring a solder reflow process for directly and electrically connecting the chip to the chip carrier via the solder bumps, the solder bumps melt when the temperature reaches a certain point, which causes collapsing, namely wetting, of the solder bumps. Such collapsing will result in an undesired bridging of neighboring solder bumps, which causes electricity failure of the package.
Please refer to FIG. 1A, which is a schematic view showing a semiconductor package disclosed in U.S. Pat. No. 6,229,220. U.S. Pat. No. 5,656,858, U.S. Pat. No. 5,466,635, and U.S. Pat. No. 6,578,754. A copper post 15 of about 30˜90 μm in height is formed on top of a metal layer 14 of a solder pad 11 of a chip 10, and a solder material 16 is formed on the copper cylinder 15. Thus at the time the chip 10 is electrically connected to a chip carrier (not shown) by means of flip chip technique, the copper post 15 effectively supports the chip 10 and prevents the package from the conventional problem of collapsing of the solder bumps.
Although the aforementioned conductive bump with high supporting capability is capable of absorbing more thermal stress when the difference between the thermal expansion coefficients of the chip and the chip carrier is high, it is undesirable to be applied to a large-sized chip, for example, a 15*15 mm chip for the following reason. In such case, some conductive bumps that have copper post are fanned around corners of the chip, and they receive relatively high thermal stress as they are positioned far from the center of the chip. Thus the relatively high stress from the copper post still not efficiently absorbed by the under bump metal layer, and therein cracks and cracked delamination C of the under bump metal layer will happen easily as illustrated in FIG. 1B.
Hence, it is a highly urgent issue in the industry for how to provide a semiconductor device that has conductive bumps, which is applicable to large-sized chips that have conductive bumps with copper post for absorbing the stress from the copper post efficiently, and further avoiding the drawbacks of cracks and delamination of the under bump metal layer.